Automatic Generation of Pausible Clock Based GALS Wrapper Circuits

In this paper we propose a method to generate pausible clock based GALS wrapper circuits from the synchronous module’s Verilog specification code automatically. We first parse the input module specification and produce wrapper circuit components based on the specification of entered synchronous module. Existing methods for generation of the wrapper circuit waste the die size because they instantiate one asynchronous port controller for each data vector. In our improved method, we reduced the number of asynchronous port controllers to simultaneous data communication links. This method will be suitable for stream based communication systems. In order to validate the proposed algorithm, we employed the wrapper circuit in Viterbi error detection and correction circuit. The results show that our improved method will reduce the area of the wrapper circuits in contrast to the previous suggested implementations.